With the continuous frequency increase of signals used in modern communication links, unwanted effects such as cross talk, false ringing, parasitic reflection, offsets occur more and more often due to the distributed nature of the media which transports these signals. In the particular case of coupled lines, a major contributor is the differential input DC offset which is the result of different amplitudes and common modes on each of the lines. For instance, according to the SCSI standard for hard-disk applications (SPI4) effective to date, data are transported at 80 MHz (frequency of the system clock). At this speed, the data integrity on the bus is high enough so as to generally not require any offset cancellation technique. On the contrary, according to the next SCSI standard to be implemented in the future (SPI5), data will be transported at 160 MHz. At such a high speed, compensation of the differential input signal DC offset becomes necessary. This differential input signal DC offset is sampled and stored in a capacitor; an analog to digital converter (ADC) then converts this value to binary digits and stores it in a register latch.
FIG. 1 illustrates the definition of the differential input signal DC offset. As shown in FIG. 1, the amplitudes and common modes of a differential signal VP-VN are different between the first half and the second half of the period T of the system clock. The differential input signal DC offset is defined as being equal to the half sum of the differential amplitude ΔV1 in the first half period and the differential amplitude ΔV2 in the second half period. The differential input signal DC offset ΔVoffset is given by: 0.5*[(VP1 +VP2)−(VN2+VN1)]=0.5*[(VP 1−VN1)+(VP2−VN2)]=0.5*[ΔV1+ΔV2]. This calculation can be performed by a sampling circuit which samples the differential input signal twice within a clock cycle and has a gain of ½.
The conventional differential input signal sampling circuit disclosed in “A ratio-independent algorithmic analog-to-digital conversion technique” (IEEE JSSC, vol 19, pp 828-836, December 1984) by P. W. Li, M. J. Chin, P. R. Gray, and R. Castello is of interest in some respects. It is constructed around a differential operational amplifier (opamp) provided with a switched-capacitor network in order to sample twice the differential input signal in four phases to generate 2*ΔV, if the input signal keeps its value at times of sampling, or [ΔV1+ΔV2] if not. However, it does not aim to calculate the differential input signal DC offset, and its gain is independent of both the opamp DC offset and the capacitor values which is a determining advantage.
FIG. 2 shows the single-ended version (simplified diagram) of this conventional differential input signal sampling circuit 20, which samples twice the input signal Vin, to generate a signal Vout=Vin+Vin=2*Vin, if input signal Vin remains unchanged during the sampling operations. The single ended version has been chosen in lieu of the differential one for the sake of simplicity of the description. Circuit 20 is organized around an operational amplifier (opamp) 21 and a switched-capacitor network comprising two capacitors C1, C2 and six switches S1-S6 connected as shown in FIG. 2. The positive input of the opamp 21 is coupled to ground. A first capacitor C1, usually referred to as the holding capacitor, is coupled to its negative input and a first node 22. A first switch S1 is coupled between first node 22 and the input signal Vin. A second switch S2 is coupled to first node 22 and ground. A second capacitor C2 is coupled between a second node 23 and the opamp 21 negative input. A third switch S3 is coupled between this negative input and the output of opamp 21. A fourth switch S4 is coupled to second node 23 and the output. A fifth switch S5 is coupled between second node 23 and ground. Finally, a sixth switch S6 is coupled to first node 22 and the output in a feedback loop. Output signal Vout that is generated by circuit 20 is independent of the opamp 21 DC offset Voff and also independent of the value of capacitors C1 and C2. Operation of circuit 20 will be described by reference to FIGS. 3a-3d. In successive drawings, the status of switches S1-S6 changes. They can be opened or closed according to the application algorithm.
Full operation of circuit 20 requires four phases: two input signal sampling and two charge transfers. Considering FIG. 3a, let us assume the input signal to be sampled Vin is equal to V1. It is easy to calculate voltage Vc1 across capacitor C1, voltage Vc2 across capacitor C2 and output voltage Vout. At the end of the first input signal sampling, we have:Vc1=V−VoffVc2=−VoffVout=VoffThe charge Q1 stored into capacitor C1 is equal to C1*(V1−Voff).
After the first sampling, the first charge transfer is performed using the configuration shown in FIG. 3b. The charge variation DQ1=C1*V1 is transferred to capacitor C2. We then have:Vc1=−VoffVc2=−Voff+V1*C1/C2Vout=V1*C1/C2The first sampling and the first charge transfer described above by reference to FIGS. 3a-3b are performed during the first half period of the system clock.
Next, the second input signal sampling is performed using the configuration depicted in FIG. 3c. After the second input sampling, we assume that Vin has changed and is now equal to V2. We have:Vc1=V2−VoffVc2=−Voff+V1*C1/C2 (Vc2 remains unchanged)Vout=Voff
Finally, the second charge transfer is performed using the configuration shown in FIG. 3d. At the end of this step, the charge Q2 stored on C2 is transferred to capacitor C1 so that we have:Vc2=−VoffDQ2=V1*C1Vc1=V2−Voff+DQ2/C1=V2−Voff+V*C1/C1=V1+V2−VoffVout=Voff+Vc1=V1+V2
The second sampling and the second charge transfer described above by reference to FIGS. 3c-3d are performed during the second half period of the system clock. The operations described above by reference to FIGS. 3a-d are thus performed at each system clock cycle.
Consequently, using circuit 20, Vout equals the sum of the two sampled input values V1 and V2. It is to be noted that Vout is independent of both the opamp 21 DC offset Voff and the values of capacitors C1 and C2, which is beneficial. However, should we consider the differential version of circuit 20 applied to the calculation of the differential DC offset ΔVoffset, it would generate a differential voltage equal to [ΔV1+ΔV2], so that it would have the inconvenience of requiring a ½ gain opamp connected in series at its outputs before obtaining the differential offset value which is equal to 0.5*[ΔV1+ΔV2].